ObsidianSolutions

Design for Testability

With rising mission critical application and competition, inserting testing capability in the design stage of the chip is ever so important. Our team have expertise in developing and integrating a complete test strategy for your ASIC design to deliver high fault coverage. Team has expertise in following area,

Test architecture
Scan & Scan-compression insertion
MBIST insertion in RTL and simulation
JTAG and BSCAN insertion, working closely with PD and Packaging team
RTL | Gate Level | Post-layout simulation
ATPG patterns generation | Simulation & diagnostics
SDC Test constraint & validation
Silicon debug – Bring up support and ATE testing
Extensive experience in bringing up chip in ATE and support till production including HTOL, ESD, functional validation in the lab.

Physical Design and Signoff

With a proven physical design flow, methodologies, and dedicated subject matter experts, we have delivered turnkey/ownership model silicon design services to many clients for successful silicon tape-outs. Our leaders/engineers experienced in Tape outs for Die size ranging from 30mm2 to 600m2, achieving optimal Die Size, Power, Area and Performance. Team has worked with multiple foundries TSMC, Samsung, GF, UMC, Tower and SMIC with technology ranging from 180nm to 3nm nodes. Expertise includes,

Floorplan & Placement
I/O Ring Planning, Bump planning, and RDL routing
Timing optimization, CTS & Routing
STA signoff (Block Level and Full Chip)
Low Power CLP checks and implementation
Power analysis (IR/EM/Signal EM/LP)
Physical verification (DRC/LVS and Antenna) signoff
ESD checks via Pathfinder or PERC
Formal verification (LEC)
Checklists signoff and QC checks process

Team also has expertise in ARM core hardening, A55, A77, A53, G77 in SF8, SF4 and N4 technology nodes

Front End Design

Obsidian’s Front-End team is experienced in various aspects of RTL design, including the design and development services of chips and systems. Collaborating with architecture teams worldwide, our teams have successfully defined systems architecture and SOC architecture in various domains. Team has developed the complete Register Transfer Language (RTL) for numerous IP blocks and SOC integration. Our team works in collaboration with Physical Design team for performance, power closure and Verification team for the test plans, coverage plans, and coverage closures.

Our Front-End engineering services addresses design and verification challenges for microchips in automotive, networking, communications, AI applications, HPC, IOT and wireless infrastructure devices. Team expertise listed below,

Architecture and Micro-architecture specifications
RTL development and verification
SOC and Sub-system Integration
System C Modelling
Synthesis, Lint, Constraints, CDC and Low power

Design Verification

Our Verification team can deliver comprehensive turnkey design verification, including complete architecture, test plans, development of new test benches, BFMs, new VIPs, scoreboards, and extensive coverage metrics. Our structured process methodologies for design verification and validation testing effectiveness ensure a bug-free product. Team has expertise in below

Architecting complex test benches using OVM, VMM and UVM
System based test case development
Test planning and scheduling using coverage driven methods
Verification from test plan to closure using functional coverage and code coverage
Expertise in RISCV and CPU based design. Have working knowledge on PCIE Gen4/5, Ethernet, USB 3.0, OTG, SATA, AMBA, SPI, UART, DDR4/5
Scoping and project planning of complex projects

Author name: ObsidianSolutions

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