Front End Design
Obsidian’s Front-End team is experienced in various aspects of RTL design, including the design and development services of chips and systems. Collaborating with architecture teams worldwide, our teams have successfully defined systems architecture and SOC architecture in various domains. Team has developed the complete Register Transfer Language (RTL) for numerous IP blocks and SOC integration. Our team works in collaboration with Physical Design team for performance, power closure and Verification team for the test plans, coverage plans, and coverage closures.
Our Front-End engineering services addresses design and verification challenges for microchips in automotive, networking, communications, AI applications, HPC, IOT and wireless infrastructure devices. Team expertise listed below,
- Architecture and Micro-architecture specifications
- RTL development and verification
- SOC and Sub-system Integration
- System C Modelling
- Synthesis, Lint, Constraints, CDC and Low power
Design Verification
Our Verification team can deliver comprehensive turnkey design verification, including complete architecture, test plans, development of new test benches, BFMs, new VIPs, scoreboards, and extensive coverage metrics. Our structured process methodologies for design verification and validation testing effectiveness ensure a bug-free product. Team has expertise in below
- Architecting complex test benches using OVM, VMM and UVM
- System based test case development
- Test planning and scheduling using coverage driven methods
- Verification from test plan to closure using functional coverage and code coverage
- Expertise in RISCV and CPU based design. Have working knowledge on PCIE Gen4/5, Ethernet, USB 3.0, OTG, SATA, AMBA, SPI, UART, DDR4/5
- Scoping and project planning of complex projects
